The present invention relates to electrical interconnect substrates and the like for integrated-circuit (IC) based electronic systems and the like. More specifically, the present invention relates to integrating discrete components such as resistors and capacitors with the interconnect substrates which are used to interconnect the electrical signals between IC chips.
In present day multichip modules (MCMs), the conventional technique for including the required amount of power supply bypass capacitance and signal-line termination resistors is by soldering discrete capacitor and resistor components on the surface of the multichip modules. An example of a typical multichip module is shown at 1 in FIG. 1. The module comprises a base substrate 5 upon which a plurality of interleaving metal layers 6 and dielectric layers 7 are formed. The top metal layer comprises a plurality of pads for making contact to integrated circuit (IC) chips 4, discrete bypass capacitors 8, and discrete termination resistors 9. The first metal layer 6 above substrate 5 and the fourth metal layer 6 above substrate 5 are the power and ground distribution planes, and are designated by the symbol xe2x80x9cDCxe2x80x9d in FIG. 1. The distribution planes are electrically coupled to the integrated circuit chips 4 by way of vias formed through dielectric layers 7. The second and third metal layers above substrate 5 generally carry signal lines between the integrated circuit chips 4 attached to the module.
The discrete capacitors 8 have their first terminals coupled to one distribution plane and their second terminals coupled to the other distribution plane, as shown in FIG. 1. The discrete resistors 7 have their first terminals coupled to a signal line and their second terminals coupled to one of the distribution planes. The purpose of the resistors is to provide a termination path to a stable voltage supply line. The selection of which distribution plane to use, either power or ground, largely depends upon the particular circuit design being implemented by multichip module 1.
A typical discrete capacitor 8 is shown in FIG. 2. It comprises a body 8A which is terminated at either end by solder coated terminals 8B and 8C. During assembly, capacitor 8 is placed upon corresponding pads of the module 1 and is soldered thereon, such as by a solder reflow process. In order to achieve a reasonable and useful level of capacitance for its intended purpose of bypassing transient current and voltage pulses on the distribution planes, capacitor 8 is rather large and bulky. Resistors 9 have similar structure and shape as capacitors 8. Referring back to FIG. 1, the discrete components 8 and 9 take up a substantial amount of surface area for the module 1, which limits the number of integrated circuits that can be mounted on the multichip module.
There are a number of disadvantages to the structure shown in FIG. 1. First, as noted above, there is an inefficient use of board space for integrated circuit (IC) chips 4 because the discrete components take up a significant amount of surface area. Second, there is a large inductance path between the bypass capacitors 8 and the power inputs to the IC chips 4. This inductance occurs in the relatively long routing path for the bypass power provided by the capacitor, which must travel from the capacitor through the vias down to the distribution planes, over the planes, and back up through the dielectric layers to the IC chips 4. A number of prior art modules have addressed this problem by forming a large area capacitor with additional metal and dielectric layers within the structure. The additional metal and dielectric layers are usually placed at the bottom next to substrate 5, and use a very thin dielectric between two metal layers. Although this structure can provide bypass capacitance with lower inductance, these capacitors have very low yield because they cover substantially the entire area of the substrate and are potentially affected by each defect on the substrate. (As a general rule, forming any structure over a large area substantially increases the risk of defects being formed during the formation of the structure.)
As an additional drawback of the structure shown in FIG. 1, the interconnect vias needed to connect a discrete resistor between a signal line and a distribution plane add parasitic capacitance and inductance to the resistor, which impedes the ability of the resistor to provide a controlled-impedance termination. Moreover, the internal structure of the resistor itself, because of its large size, introduces additional parasitic capacitances and inductances. These parasitic components severely impede the discrete resistor""s ability to act as good high-frequency signal terminator, thereby limiting the overall signal transmission performance of the module.
Accordingly, there are several drawbacks with present day multichip modules which hinder their ability to achieve high levels of density and speed. The present invention is directed toward addressing these drawbacks.
The present invention addresses these drawbacks by providing a modularly constructed multichip module. Starting with a base substrate, a plurality of miniature capacitor substrates and/or miniature resistor substrates are assembled and attached to the base substrate, preferably in a regular array pattern. Power supply substrates (xe2x80x9cpower barsxe2x80x9d) are preferably attached to the base substrate along with the miniature substrates. All of the components so attached are preferably pretested and have thicknesses which are close to one another. The pretesting substantially increases the manufacturing yield of the module. The gaps between the miniature substrates and power supply substrates are filled with a polymer material, such as a powder-filled polyimide precursor. Thereafter, a dielectric layer is formed over the components to provide a more planar surface. The dielectric layer is preferably planarized, such as by a chemical mechanical polishing process, to provide for a more planar layer. Thereafter, a plurality of interleaving metal and dielectric layers are formed over the assembled components to provide power distribution planes and signal lines. Miniature capacitor substrates are preferably positioned underneath respective integrated circuit chips to provide very short paths and very small inductance to the integrated circuit chips. In a similar manner, the miniature resistor substrates are placed close to the desired point of signal termination, which is typically at the interconnect pad of an IC chip. As an important feature, the miniature substrates enable the resistors to be implemented in a technology which provides significantly less parasitic capacitance and inductance. As another important feature, because the capacitors and resistors are below the integrated circuit chips, they do not occupy valuable surface area of the module. This arrangement enables a much higher density of integrated circuit chips to be formed over the surface of the multichip module.
As an additional feature and advantage of the present invention, some of the resistor elements may be configured in selected embodiments of the present invention to selectively heat the interconnect pads under a selected IC chip to melt the solder bonds and enable easy removal of the IC chip. During operation of the module, one or more of the IC chips may occasionally fail and require replacement. This feature of the present invention enables easy replacement of failed chips.
Accordingly, it is an object of the present invention to provide a high value capacitance in close proximity to an integrated circuit chip in a multichip module with a minimal amount of supply line inductance.
It is yet another object of the present invention to reduce the amount of parasitic capacitance and inductance associated with the signal termination resistors in multichip modules.
It is still a further object of the present invention to enable the manufacture of multichip modules with high bypass capacitance without degrading manufacturing yields.
It is yet a further object of the present invention to increase the density of integrated circuit chips for multichip modules.
These and other objects of the present invention will become apparent to those skilled in the art from the following detailed description of the invention, the accompanying drawings, and the appended claims.